How Synchronous counter works | Synchro counter applications

How Synchronous counter works | Synchro counter applications

A counter can be defined as a device that is used to count a particular event based on the events that occurred. The main role of this counter within a computer hardware or digital logic system is to count and store the number of times a process or event occurs based on the CLK signal. There are different types of counters like synchronous counter, asynchronous counter, synchronous nodes, asynchronous nodes, synchronous up-down counter, and asynchronous top-down counter.

The most common type of counter is a sequential logic circuit including one CLK and several outputs. Here the outputs are denoted in binary or decimal by binary code. Each CLK signal either boosts the number or decreases the number. This article covers an overview of the async counter and its operation with applications.

What is a synchronous counter?

Synchronous counter can be defined as a counter that uses a clock signal to shift their transmission. Therefore, these counters mainly depend on the clock input to modify the status values. In this counter all flip flops (FFs) are associated with the same clock signal to activate simultaneously. The alternate name of this counter is synchronous counter as there is no ripple effect and propagation delay in these counters.

Compared with the synchronous design, the asynchronous type design is very simple but the asynchronous counter has a limitation of the maximum operating frequency. To overcome this limitation, these counters are primarily designed by providing synchronous timing so that the output changes in synchronization through the clock input.

Synchronous counter circuit diagram

The design and operation of the synchronous counter is explained below. The circuit diagram of the 3-bit asynchronous counter is shown below and this circuit is designed with 2 logic gates, 3 J-K FFs and a CLK signal which is used to enable the Flip Flop.

Here, an active high signal is supplied to the input pin of flip flop A. Thus, switching takes place at the shorted edge of each CLK input. Similarly, the AND gate is provided to the flip flop -B as the output depends mainly on the inputs and outputs of the previous FFs in this case. Once the AND gate is triggered, the flip-flop B will simply switch once the output of the flip-flop is high.

In this way, the input of the flip-flop C will be the second AND output of the gate. Therefore, the C flip-flop is switched once logic gate A2 is activated. When the output of logic gate A1 and Flip Flop-B is high, logic gate A2 will be energized.

Let's discuss the operation of a 3-bit synchronous counter. At the beginning of the circuit the flip-flops are arranged at 0, then the outputs of the three flip-flops are zero as QCQBQA = 000. But at the drop edge of the initial CLK signal, the output of the A flip-flop switches from zero to one. So in B & FF-C flip-flops no change will occur because these two input terminals are 0 until the next CLK signal arrives.

Thus, when the first CLK signal is presented, the output of the flip-flops will be QCQBQA = 001. Before the second clock signal is applied, both FF inputs will be like A & B 1 due to the higher output of the A1 gate. So, at the edge of the second CLK signal drop, both Flip Flops will switch again. So this will change the FFA output from one to zero and the FFB output from zero to one. Therefore, the output will be 010; Both logic gates such as A1 and A2 will be turned off.

Once the third clock signal is applied, the flip-flop-A output will be switched and logic gates A1 and A1 will turn on, so the output will be 011. Once the fourth clock signal is applied, all three FF inputs will be loud in the circuit. So the falling edge of the fourth flip-flop will switch all the outputs of the flip-flop, thus changing QA & QB to 0 & QC to 1. So the total o/p of the CLK's own signal will be 100, so the logic gates A1 & A2 will be off.

As soon as the next CLK signal appears, then at the drop edge of the fifth CLK signal, the FF-A output will again switch from low to high. As a result, the output of QCQBQA will be 10, so logic gates A1 and A2 will be activated.

Once the sixth CLK signal is applied, flip-flop A at the edge of the fall to switch from 1 to 0. Also the input to flip-flop B is high, so its output switches from 0 to 1. Thus, in this case, QCQBQA would be 110. Further , this process will continue and at the bottom edge of the 8th CLK signal all output FFs such as QCQBQA will be reset to 000.

In synchronous counters, it is important that all FFs within the circuit are reset at once. So the counter setting time is equal to each flip-flops propagation delay within the circuit. Therefore, this counter can be controlled by a high-frequency CLK signal.

The truth table of the 3-bit async counter is shown below based on the above explanation.

CLK

QC QB QA

decimal equivalent

First

0 0 0 0

first landing edge

0 0 1 1

second falling edge 0 1 0

2

The third falling edge 0 1 1

3

4th falling edge

1 0 0 4

5 edge falling 1 0 1

5

  VI Falling Edge

1

1 0 6

7th Falling Edge 1 1 1

7

8 edge falling 0 0 0

0

The synchronous counter timing diagram is shown below.

Types of synchronous counters

In digital electronics, there are various types of synchronous counters available such as binary counters, 4-bit synchronous UP, 4-bit synchronous DOWN, 4-bit synchronous UP or DOWN, BCD counter, synchronous contract counter, 2-bit, 3-bit, loadable, Johnson counter , the loop counter. Some of them are discussed below.

Dual counters

A binary counter is an electronic circuit made of flip-flops in which the output of a flip-flop is provided as an input to the next flip-flop in series. Depending on the connection of flip flops (FFs) in the circuit, either a synchronous or asynchronous binary counter can be used. In a synchronous counter, all filters are energized by a similar CLK signal.

The asynchronous counter is known as the ripple counter. In this type of counter the CLK signal is given directly to the first FF and then sent with a propagation delay to another FF.

4- bit synchronous counter

A 4-bit asynchronous counter can be designed like a 3-bit asynchronous counter but the difference is in the number of flip flops used. In this counter, four JK slippers are used for the design. The main reason to use this permutation is to switch its state if both inputs are high based on the CLK signal.

An external CLK signal is given to all four bumps in parallel. This counter includes 16 output states where the count is from 0000 to 1111. Compared to 3-bit, the timing scheme of this counter and its operation are also the same.

4- bit synchronous bottom counter

The main function of this counter is to count numbers in descending order. Compared with the upper counter, the lower counter is also the same but it should reduce the count. Thus, the input of the JK flip-flop is connected to the Q' direction and the same external CLK signal is connected to the four flip-flops inside the circuit.

When this counter counts down the string, initially all FF inputs will be in high because they have to count down the string. So, it will start with 1111 and stop with 0000 as a higher counter. In this type of counter it should be noted that if the forward permutation generates a logic low at its output, the previous permutation will simply be toggled.

2-bit synchronous counter

A 2-bit synchronous counter is designed with two JK-Flip flaps and two Feynman gates. Here, a Feynman gate is an unsupervised CNOT or gate that is used to transcribe a signal because in reversible logic circuits, outflow is not allowed. So this gate is used like a ventilation gate to copy a signal.

The CLK input is given to a Feynman gate where the output is allied to another gate as the input and also connected to the reversible JK flip flop as the CLK input.

Up/down synchronous counter or bidirectional counter

The synchronous counter is designed to act as an up/down counter using control signals as it is capable of counting in any direction so it is known as a bi-directional counter. In this counter the JK flip-flop is used as a T flip-flop to store the bits.

For example, a 3-bit bidirectional counter has 8 possible output conditions. Depending on the control input, it will count in any direction. 7 to 0.

Here, the direction of counter action will be determined by a control input. Once the control input is 1, then it will turn off gates 2 and 4 AND and enable gates 1 and 3. So in this case this counter will start counting in an ascending direction.

Pros - Cons

The advantages and disadvantages of a synchronous counter include the following.

Compared with asynchronous, it is easy to design

works simultaneously.

There is no propagation delay associated with it.

String counting is controlled by logic gates,

faster operation

The main drawback of the async counter is that it needs a lot of extra logic to implement.

All swing face is driven by a single or combined CLK signal

They need large components and electrical circuits.

This counter uses a complex logic circuit and the incremental number of states.

Applications

Synchronous counter applications include the following.

Machine motion control

Engine RPM counter

Rotate Shaft Encoder

pulse generators

digital clock

Alarm systems

digital clock

1). Which FF is used in a synchronous counter?

The synchronous counter uses edge-operated FFs to change conditions on the rising edge (positive edge) or lower edge (negative edge) of the CLK signal on the control input.

2). What are synchronous devices?

Devices that communicate synchronously with each other through a separate timing-recording channel are known as synchronous devices.

3). How many states will there be in a 4-bit synchronous counter?

In a 4-bit asynchronous counter, the total number of states is 2^4 = 16 states.

4). What is a 3-bit synchronous bottom counter?

The 3-bit synchronous bottom counter is designed with an AND gate and three T-shape skids. These three bumps are negative edge actuated and the outputs of the FFs will change their effect synchronously. Here, the inputs of 'T' for all flip-flops are 1, Q0′ and 'Q1′ Q0 correspondingly

Thus, this is all about an overview of the synchronous counter that can be made with D-type or Toggle flip-flops. Compared to asynchronous, it is very easy to design. As the name implies, the CLK inputs of all flip-flops are mutually registered with the same CLK signal so that all output states change or shift simultaneously. Here's a question for you, what is a synchronous nodes counter?